Senior Analog EDA Engineer | $55K – $65K | Cadence Virtuoso
- Bengaluru, Hybrid
Full Job Description
About the Company
A deep-tech semiconductor company building next-generation analog and mixed-signal design infrastructure using GenAI. The focus is on scaling analog chip design by automating traditionally manual, experience-heavy workflows. The team works closely with founders and domain experts who have taken products from first silicon to high-volume production.
This is a product-driven environment where engineering depth, clarity of thought, and long-term technical ownership matter.
Role Overview
The Senior Analog EDA Engineer will own automation across the analog design lifecycle, with a strong emphasis on Cadence Virtuoso, OpenAccess, and SKILL-based flows. The role sits at the intersection of analog design, EDA infrastructure, and AI-assisted workflows, enabling faster, more reliable chip development.
This position is hands-on, system-level, and built for engineers who enjoy solving hard tooling problems at scale.
Key Responsibilities
- Design, build, and maintain end-to-end PDK/CDK automation pipelines
- Develop and optimize SKILL scripts within Cadence Virtuoso environments
- Work deeply with OpenAccess databases for layout, schematic, and flow automation
- Enable reusable, scalable analog design flows across multiple process nodes
- Collaborate with analog designers to translate manual workflows into robust tooling
- Support integration of GenAI-assisted techniques into analog EDA systems
- Improve design productivity, consistency, and tape-out readiness
Required Expertise
- Deep hands-on experience with Cadence Virtuoso
- Strong knowledge of OpenAccess architecture and APIs
- Advanced proficiency in SKILL scripting
- Proven experience building and maintaining PDK/CDK automation
- Strong understanding of analog and mixed-signal design flows
- Ability to own systems end-to-end, from concept to production use
What Sets This Role Apart
- Direct exposure to GenAI-driven analog design workflows
- Ownership over core EDA infrastructure, not peripheral tooling
- Work alongside founders and engineers with real tape-out and scale experience
- Problems rooted in production silicon, not experimental demos
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