Senior EDA Engineer (Cadence Virtuoso) | GenAI-Powered Semiconductor Platform | Analog & Custom IC Design
- 55K–65K
- Bengaluru, India, On-site (Bengaluru)
Full Job Description
GenAI-Powered Circuit Assistant
Revolutionizing the IC design cycle with an intelligent copilot that accelerates development, slashes errors, and automates end-to-end design reviews—all in one seamless workflow.
About the Company
A founder-led semiconductor startup, backed by leaders who have scaled deep-tech companies from zero to acquisition. The team is building a GenAI-powered analog design platform that blends deep EDA expertise with AI-driven automation to modernize analog and mixed-signal IC development. Fast execution, real ownership, and high technical depth define the culture.
Role Overview
Seeking a Senior EDA Engineer with strong hands-on expertise in Cadence Virtuoso, SKILL scripting, and OpenAccess (OA) to build robust automation and production-grade design flows. This role works closely with EDA and AI teams to power a next-generation AI copilot for analog IC design.
What You’ll Do
Build and optimize analog & mixed-signal IC flows in Cadence Virtuoso
Develop SKILL scripts for schematic, layout, verification, and environment automation
Customize and manage CDFs for foundry PDK/CDK libraries
Use OpenAccess APIs (C++ / Python / Tcl) to manipulate schematic, layout, and library data
Integrate, validate, and debug PDKs/CDKs, pCells, DRC/LVS decks, and models
Enable schematic–layout synchronization and OA-based automation workflows
Partner with AI engineers to embed EDA tooling into a GenAI circuit copilot
What You Bring
3–8 years of hands-on experience with Cadence Virtuoso
Strong SKILL scripting expertise
Solid experience with OpenAccess (OA) schemas and APIs
Deep understanding of foundry PDK/CDK structures
Experience automating EDA workflows using SKILL, Tcl, or Python
Strong grasp of LVS, schematic-driven layout, and OA consistency
Linux/UNIX proficiency and EDA version control experience
Comfort thriving in a fast-moving startup environment
Nice to Have
Prior experience at Cadence or leading semiconductor firms
Exposure to Spectre, ADE, and analog verification flows
Understanding of analog device physics
Familiarity with AI/ML-enabled EDA tools
Why This Role
Greenfield platform. Deep technical ownership. Real impact on how analog ICs are designed—with AI at the core.
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